Invited talk on statistical circuit simulation

On November 11, 2021, Prof. Sato gave the following invited talk on statistical circuit simulation at a workshop jointly organized by the Silicon Materials and Devices (SDM) Society of the Institute of Electronics, Information and Communication Engineers (IEICE) and the Silicon Technology Section of the Japan Society of Applied Physics.

  • Takashi Sato, Hiroki Tsukamoto, Song Bian, and Michihiro Shintani, “Non-normal model parameter generation for variation-aware circuit simulation (invited),” IEICE Technical report, SDM2021-54, vol. 121, no. 235, pp.7-12, November 2021.

Accepted for DATE 2022

The paper below is accepted for Design, Automation and Test in Europe Conference (DATE). This research was performed as the joint project with Hitachi Ltd.

Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, “Estimating Vulnerability of All Model Parameters in DNN with a Small Number of Fault Injections,” Proceedings of Design, Automation and Test in Europe Conference (DATE), to appear.

Paper accepted: APEC2022

The following paper has been accepted for presentation at the IEEE Applied Power Electronics Conference and Exposition (APEC) 2022.  APEC is one of the top conferences in power electronics.

  • Kyohei Shimozato, Michihiro Shintani, and Takashi Sato, “Adaptive outlier detection for power MOSFETs based on Gaussian process regression,” in Proc. IEEE Applied Power Electronics Conference and Exposition (APEC), March 2022. (accepted for presentation) arXiv

Accepted for BMVC 2021

The paper below has been accepted by British Machine Vision Conference. This research is a result of the CREST project on optical neural networks.

A. Lopez, M. Hashimoto, M. Motomura, and J. Yu, “Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks,” Proceedings of British Machine Vision Conference (BMVC), to appear.

Paper accepted: WAHC2021

The following paper has been accepted to ACM Workshop on Encrypted Computing & Applied Homomorphic Cryptography (WAHC).

Kotaro Matsuoka, Yusuke Hoshizuki, Takashi Sato and Song Bian, “Towards better standard cell library: Optimizing compound logic gates for TFHE,” in Proc. ACM Workshop on Encrypted Computing & Applied Homomorphic Cryptography (WAHC), November 2021. (accepted for presentation)

Best Paper Award, the Virtual Reality Society of Japan

Assistant Prof. Shirai received Best Paper Award from the Virtual Reality Society of Japan regarding the paper below (2021/9/13).

Y. Itoh, Y. Ishihara, R. Shirai, K. Fujita, K. Takashima, and T. Onoye, “StickyTouch: A Touch Display with Controllable Local Adhesion,” Transactions of the Virtual Reality Society of Japan (in Japanese), Vol. 25, No. 4, pp. 384-393, 2020.

Paper accepted: Transactions of the Virtual Reality Society of Japan

The paper below has been accepted by Transactions of the Virtual Reality Society of Japan. The first author is Ms. Suzunaga who completed master’s degree at Osaka University in March 2021. This work was carried out at Osaka University with Tohoku University,

S. Suzunaga, K. Fujita, R. Shirai, and Y. Itoh, “CoiLED Display: Striped Flexible Displays Windable Around Objects, ” Transactions of the Virtual Reality Society of Japan (in Japanese), accepted, to appear.

Paper accepted: IEEE Journal of Solid-State Circuits

The paper below has been accepted for publication by IEEE Journal of Solid-State Circuits.
This research is a result of the CREST project on via-switch FPGA.

X. Bai, N. Banno, M. Miyamura, R. Nebashi, K. Okamoto, H. Numata, N. Iguchi, M. Hashimoto, T. Sugibayashi, T. Sakamoto, and M. Tada, “Via-Switch FPGA: 65nm CMOS Implementation and Evaluation,” IEEE Journal of Solid-State Circuits, in press.