The following paper has been accepted for publication in IEEE Open Journal of Circuits and Systems (OJCAS).
H. Tagata, T. Sato, and H. Awano, “Double MAC on a Cell: A 22-nm 8T-SRAM based Analog In-Memory Accelerator for Binary/Ternary Neural Networks Featuring Split Wordline,” in IEEE Open Journal of Circuits and Systems, accepted.
