Paper accepted: IEEE Transactions on Circuits and Systems II

The following paper is accepted by IEEE Transactions on Circuits and Systems II. This is a collaborative work with Southern University of Science and Technology.

Q. Cheng, L. Dai, M. Huang, A. Shen, W. Mao, M. Hashimoto, H. Yu, “A Low-Power Sparse Convolutional Neural Network Accelerator with Pre-Encoding Radix-4 Booth Multiplier,” in IEEE Transactions on Circuits and Systems II: Express Briefs, doi: 10.1109/TCSII.2022.3231361.

IRPS 2023

The following paper has been accepted. It is the result of joint research with JAEA, the University of Tokyo, and AIST, and will be presented in Monterey, CA in March 2023.

K. Takami, Y. Gomi, S. Abe, W. Liao, S. Manabe, T. Matsumoto, and M. Hashimoto, “Characterizing SEU Cross Sections of 12- and 28-nm SRAMs for 6.0, 8.0, and 14.8 MeV Neutrons,” Proceedings of International Reliability Physics Symposium (IRPS), to appear.