Category: Publication

The following paper has been accepted for publication in Japanese Journal of Applied Physics (JJAP). This is a progress review article associated with the plenary talk given by Prof. Hashimoto at International Conference on Memristive Materials, Devices & Systems (MEMRISYS) 2021.

M. Hashimoto, X. Bai, N. Banno, M. Tada, T. Sakamoto, J. Yu, R. Doi, H. Onodera, T. Imagawa, H. Ochi, K. Wakabayashi, Y. Mitsuyama, and T. Sugibayashi, “Via-Switch FPGA with Transistor-Free Programmability Enabling Energy-Efficient Near-Memory Parallel Computation,” Japanese Journal of Applied Physics, in press, https://doi.org/10.35848/1347-4065/ac6b81.

The following paper has been accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). This research was closely discussed at the Technical University of Munich in the early days of this research.

• Grace Li Zhang, Bing Li, Xing Huang, Xunzhao Yin, Cheng Zhuo, Masanori Hashimoto, Ulf Schlichtmann, “VirtualSync+: Timing Optimization with Virtual Synchronization,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2022.3153433.

The following paper has been accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). This paper is a summary of the research results developed by a former student of our laboratory, who further extended the results of his research when he was a master’s course student.

The following paper has been accepted for publication in Japanese Journal of Applied Physics (JJAP). This is a joint work with Rohm Co. Ltd.

• Yasuhiro Ogasahara, Kazunori Kuribara, Kunihiro Ohshima, Zhaoxing Qin, and Takashi Sato, “Yield and Leakage Current of Organic Thin-Film Transistor Logic Gates toward Reliable and Low-Power Operation of Large-Scale Logic Circuits for IoT Nodes,” Japanese Journal of Applied Physics (JJAP), Vol.61, December 2021. doi:10.35848/1347-4065/ac44cf

The following paper has been accepted for publication in Japanese Journal of Applied Physics (JJAP). This is an outcome of the joint work with National Institute of Advanced Industrial Science.

• Yasuhiro Ogasahara, Kazunori Kuribara, Kunihiro Ohshima, Zhaoxing Qin, and Takashi Sato, “Yield and Leakage Current of Organic Thin-Film Transistor Logic Gates toward Reliable and Low-Power Operation of Large-Scale Logic Circuits for IoT Nodes,” Japanese Journal of Applied Physics (JJAP), Vol.61, December 2021. doi:10.35848/1347-4065/ac44cf

The research results of the joint research with Kochi University of Technology conducted within the framework of OPERA will be published in IEEE Transactions on Nuclear Science.

T. Tanaka, W. Liao, M. Hashimoto, and Y. Mitsuyama, “Impact of Neutron-Induced SEU in FPGA CRAM on Image-Based Lane Tracking for Autonomous Driving: from Bit Upset to SEFI and Erroneous Behavior,” IEEE Transactions on Nuclear Science, accepted for publication.

IThe following paper has been accepted for publication in IEEE Transactions on Power Electronics (TPEL).

Michihiro Shintani, Aoi Ueda, and Takashi Sato, “Accelerating Parameter Extraction of Power MOSFET Models Using Automatic Differentiation,” IEEE Transactions on Power Electronics (TPEL), (accepted for publication).

The paper below has been accepted by Transactions of the Virtual Reality Society of Japan. The first author is Ms. Suzunaga who completed master’s degree at Osaka University in March 2021. This work was carried out at Osaka University with Tohoku University,

S. Suzunaga, K. Fujita, R. Shirai, and Y. Itoh, “CoiLED Display: Striped Flexible Displays Windable Around Objects, ” Transactions of the Virtual Reality Society of Japan (in Japanese), accepted, to appear.

The paper below has been accepted for publication by IEEE Journal of Solid-State Circuits.
This research is a result of the CREST project on via-switch FPGA.

X. Bai, N. Banno, M. Miyamura, R. Nebashi, K. Okamoto, H. Numata, N. Iguchi, M. Hashimoto, T. Sugibayashi, T. Sakamoto, and M. Tada, “Via-Switch FPGA: 65nm CMOS Implementation and Evaluation,” IEEE Journal of Solid-State Circuits, in press.