Category: Conference / Workshop

Conference / Workshop

Paper accepted to Symposium on VLSI Technology and Circuits

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The following paper has been accepted to the Symposium on VLSI Technology and Circuits. We will be presenting it in Kyoto this June

Quan Cheng, Qiufeng Li, Zhengke Yang, Zhen Kong, Gaoqiang Niu, Yuan Liang, Jiamin Li, Jeong Hoan Park, Wang Liao, Hiromitsu Awano, Takashi Sato, Longyang Lin, Masanori Hashimoto, “A Radiation-Hardened Neuromorphic Imager with Self-Healing Spiking Pixels and Unified Spiking Neural Network for Space Robotics,” Digest of Symposium on VLSI Technology and Circuits, to appear.

Conference / Workshop

CICC 2025

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At the Custom Integrated Circuits Conference (CICC 2025) held in Boston, USA from April 14th to April 16th, 2025, Hashimoto presented the research findings on behalf of Cheng (presentation date: April 16th, 2025).

Q. Cheng, Q. Li, W. Dong, M. Zhang, R. Zhang, M. Huang, H. Yu, Y. Shi, H. Awano, T. Sato, L. Lin, and M. Hashimoto, “A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-On-Chip Towards In-Orbit Computing,” Proceedings of IEEE Custom Integrated Circuits Conference (CICC), 2025.

Conference / Workshop

Papers accepted for IEEE International NEWCAS Conference

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The following papers have been accepted to IEEE International NEWCAS Conference, to be held in Paris, France, in Jun 2025.

  • Hiroaki Kitaike, Ruilin Zhang, Hironori Tagawa, Kento Okamura, Kei Awano, You Wu, Teruaki Ono, Kohei Sakamoto, Jin Nakamura, Masaya Kaneko, Yuta Kimura, Hiroaki Nakamura, Kunyang Liu, Shufan Xu, Hirofumi Shinohara and Kiichi Niitsu, “A 22nm CMOS 0.000005mm2 0.25V 2.3pW ISFET Front-End Using Low-Gate-Leakage Thick-Gate- Oxide Transistors for Energy-Efficient Small- Formfactor Ph Monitoring,”
Conference / Workshop

DATE 2025

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Hashimoto presented research findings at the Design, Automation and Test in Europe Conference (DATE 2025) held in Lyon, France from March 31st to April 2nd, 2025 (presentation date: April 2nd, 2025).

Q. Cheng, W. Liao, R. Zhang, H. Yu, L. Lin, and M. Hashimoto, “HachiFI: a Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact Evaluation,” Proceedings of Design, Automation and Test in Europe Conference (DATE), March 2025.

Conference / Workshop

WACV2025

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At the IEEE/CVF Winter Conference on Applications of Computer Vision (WACV), held in Tucson, Arizona, USA, from February 27 to March 4, 2025, D2 student Shaoxiong Zhang presented his research findings (presentation was on March 1).

  • Shaoxiong Zhang, Hiromitsu Awano, and Takashi Sato, “GaitCloud: Leveraging spatial-temporal information for LiDAR-base gait recognition with a true-3D gait representation,” in Proc. IEEE/CVF Winter Conference on Applications of Computer Vision (WACV), pp.2849-2858, February 2025.
Conference / Workshop

Papers accepted for DAC2025

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The following papers have been accepted to Design Automation Conference (DAC), to be held in San Francisco, CA, in Jun 2025.

  • Hiroto Tagata, Takashi Sato and Hiromitsu Awano, “Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline Accumulation,” Design Automation Conference (DAC), Jun 2025, to appear. (regular paper acceptance ratio: 420/1862=22.5%)
  • Xinyi Guo, Hiromitsu Awano and Takashi Sato, “Weighted Range-Constrained Ising-Model Decoder for Quantum Error Correction,” Design Automation Conference (DAC),Jun 2025, to appear. (regular paper acceptance ratio: 420/1862=22.5%)
Award/Conference / Workshop

ASP-DAC2025

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At Asia and South Pacific Design Automation Conference (ASP-DAC 2025) held at the National Museum of Emerging Science and Innovation (Miraikan) in Japan from January 20 to January 23, 2025, the following members made presentation:

  • Masanori Hashimoto, Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi, Kozo Takeuchi, “ML-assisted SRAM Soft Error Rate Characterization: Opportunities and Challenges,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.379-384, January 2025.
  • Tomonari Tanaka, Takumi Uezono, Kohei Suenaga, Masanori Hashimoto, “Hardware Error Detection with In-Situ Monitoring of Control Flow-Related Specifications,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.966-973, January 2025.
  • Takuma Kawakami, Takashi Sato, Hiromitsu Awano, “Random Telegraph Noise Observed on 65-nm Bulk pMOS Transistors at 3.8K,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.1438-1443, January 2025.

Additionally, the following poster presentations were made during the co-located Work-in-Progress session:

  • Masami Utsunomiya, Hiroya Murata, Hiromitsu Awano, Takashi Sato, “Hardware Reservoir Using Transistor Variation Based on a 180nm Node Prototype Chip.”
  • Wakahiro Ohara, Takashi Sato, Hiromitsu Awano, “Cryo-CMOS Surface Code Decoder for Fault-Tolerant Quantum Computers.”
  • Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi, Kozo Takeuchi, Masanori Hashimoto, “Event-Wise Accurate Single-Event Upset Discrimination with Active Learning and Adaptive Hyperparameter Tuning.”

The first poster presentation received the Poster Award, and the second poster presentation won the Best Poster Award.

Conference / Workshop

Paper accepted at CICC 2025

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The following paper has been accepted for presentation at the IEEE Custom Integrated Circuits Conference (CICC) 2025. We will be presenting our findings in Boston in April.

Q. Cheng, Q. Li, W. Dong, M. Zhang, R. Zhang, M. Huang, H. Yu, Y. Shi, H. Awano, T. Sato, L. Lin, and M. Hashimoto, “A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-On-Chip Towards In-Orbit Computing,” Proceedings of IEEE Custom Integrated Circuits Conference (CICC), to appear.

集積システム工学講座 / Integrated Systems Engineering Laboratory
(佐藤、新津、橋本研 / Sato, Niitsu, Hashimoto Lab.)