Category: Conference / Workshop

Award/Conference / Workshop

ASP-DAC2025

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At Asia and South Pacific Design Automation Conference (ASP-DAC 2025) held at the National Museum of Emerging Science and Innovation (Miraikan) in Japan from January 20 to January 23, 2025, the following members made presentation:

  • Masanori Hashimoto, Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi, Kozo Takeuchi, “ML-assisted SRAM Soft Error Rate Characterization: Opportunities and Challenges,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.379-384, January 2025.
  • Tomonari Tanaka, Takumi Uezono, Kohei Suenaga, Masanori Hashimoto, “Hardware Error Detection with In-Situ Monitoring of Control Flow-Related Specifications,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.966-973, January 2025.
  • Takuma Kawakami, Takashi Sato, Hiromitsu Awano, “Random Telegraph Noise Observed on 65-nm Bulk pMOS Transistors at 3.8K,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.1438-1443, January 2025.

Additionally, the following poster presentations were made during the co-located Work-in-Progress session:

  • Masami Utsunomiya, Hiroya Murata, Hiromitsu Awano, Takashi Sato, “Hardware Reservoir Using Transistor Variation Based on a 180nm Node Prototype Chip.”
  • Wakahiro Ohara, Takashi Sato, Hiromitsu Awano, “Cryo-CMOS Surface Code Decoder for Fault-Tolerant Quantum Computers.”
  • Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi, Kozo Takeuchi, Masanori Hashimoto, “Event-Wise Accurate Single-Event Upset Discrimination with Active Learning and Adaptive Hyperparameter Tuning.”

The first poster presentation received the Poster Award, and the second poster presentation won the Best Poster Award.

Conference / Workshop

Paper accepted at CICC 2025

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The following paper has been accepted for presentation at the IEEE Custom Integrated Circuits Conference (CICC) 2025. We will be presenting our findings in Boston in April.

Q. Cheng, Q. Li, W. Dong, M. Zhang, R. Zhang, M. Huang, H. Yu, Y. Shi, H. Awano, T. Sato, L. Lin, and M. Hashimoto, “A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-On-Chip Towards In-Orbit Computing,” Proceedings of IEEE Custom Integrated Circuits Conference (CICC), to appear.

Conference / Workshop

IDW2024

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Prof. Sato gave an invited talk at International Display Workshops (IDW) 2024 held at the Sapporo International Convention Center from December 4 to 6, 2024. (The invited talk was on December 5).

  • Takashi Sato, Kunihiro Oshima, and Zhaoxin Qin, “Low voltage DNTT-based organic TFTs: layout structure, device characteristics, and its application to circuit design (invited),” in Proc. International Display Workshops (IDW), pp.172-175, Dec. 2024.
Conference / Workshop

A-SSCC2024

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In A-SSCC 2024, which was held at the Hiroshima International Conference Center from November 18 to 21, 2024, Prof. Sato participated as one of the panelists in the panel discussion “AI-Driven IC Design: Opportunities and Challenges”. (The panel discussion was held on November 20).

Quan Cheng, who completed their doctoral program in September 2024, presented the following paper (presentation date: November 20).
Q. Cheng, L. Lin, M. Huang, Q. Li, Z. Yang, L. Dai, H. Yu, Y. Chen, Y. Shi, and M. Hashimoto, “A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping,” Technical Digest of Asian Solid-State Circuits Conference (A-SSCC), 2024.

Conference / Workshop

ICCD 2024

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At the International Conference on Computer Design (ICCD), held in Milan, Italy, from November 18 to 20, 2024, D2 student Zhang presented his research findings (presentation date: November 18).

M. Zhang, Q. Cheng, H. Awano, L. Lin, and M. Hashimoto, “S3M: Static Semi-Segmented Multipliers for Energy-Efficient DNN Inference Accelerators,” Proceedings of IEEE International Conference on Computer Design (ICCD), 2024.

Conference / Workshop

DATE 2025

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The following paper has been accepted for DATE 2025. The results will be presented in Lyon in March 2025.

Quan Cheng, Wang Liao, Ruilin Zhang, Hao Yu, Longyang Lin and Masanori Hashimoto, HachiFI: A Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact Evaluation, Proc. Design, Automation and Test in Europe Conference (DATE), to appear.