Category: Award

Award

ISSCC 2026 Silkroad Award

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D3 Student Xu-san’s paper won the Silkroad Award at the ISSCC 2026.
Since Xu-san was unable to attend the conference, Assistant Professor Liu attended the ceremony and accepted the award on her behalf.

“A Sub-Threshold All-NMOS Reconfigurable PUF with Secure Configuration Selection for Stable 6-Bits/Cell”

Authors: Shufan Xu*, Kunyang Liu*, Lando Chan, Hironori Tagawa, Hirofumi Shinohara, and Kiichi Niitsu (*Equally Credited Authors)

Award

The Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science and Technology

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Hashimoto received the award below (April 15, 2025).

The Commendation for Science and Technology by the Minister of Education,
Culture, Sports, Science and Technology
Awards for Science and Technology (Research Category)

The research topic for the award is as follows:

“Research on High-Reliability Integrated Circuit Design for Overcoming Soft Errors.”

Award

IEEE EDS Japan Chapter Student Award (VLSI)

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M1 Kitaike-Kun was awarded IEEE EDS Japan Chapter Student Award (VLSI)!

M1北池君がIEEE EDS Japan Chapter Student Award (VLSI)を受賞されました。

Hiroaki Kitaike, “A 0.9-2.6pW 0.1-0.25V 22nm 2-bit Supply-to-Digital Converter Using Always- Activated Supply-Controlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed Time-Stamped Bio-Recording”, IEEE EDS Japan Chapter Student Award (VLSI), Feb.2025.

Award/Conference / Workshop

ASP-DAC2025

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At Asia and South Pacific Design Automation Conference (ASP-DAC 2025) held at the National Museum of Emerging Science and Innovation (Miraikan) in Japan from January 20 to January 23, 2025, the following members made presentation:

  • Masanori Hashimoto, Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi, Kozo Takeuchi, “ML-assisted SRAM Soft Error Rate Characterization: Opportunities and Challenges,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.379-384, January 2025.
  • Tomonari Tanaka, Takumi Uezono, Kohei Suenaga, Masanori Hashimoto, “Hardware Error Detection with In-Situ Monitoring of Control Flow-Related Specifications,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.966-973, January 2025.
  • Takuma Kawakami, Takashi Sato, Hiromitsu Awano, “Random Telegraph Noise Observed on 65-nm Bulk pMOS Transistors at 3.8K,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.1438-1443, January 2025.

Additionally, the following poster presentations were made during the co-located Work-in-Progress session:

  • Masami Utsunomiya, Hiroya Murata, Hiromitsu Awano, Takashi Sato, “Hardware Reservoir Using Transistor Variation Based on a 180nm Node Prototype Chip.”
  • Wakahiro Ohara, Takashi Sato, Hiromitsu Awano, “Cryo-CMOS Surface Code Decoder for Fault-Tolerant Quantum Computers.”
  • Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi, Kozo Takeuchi, Masanori Hashimoto, “Event-Wise Accurate Single-Event Upset Discrimination with Active Learning and Adaptive Hyperparameter Tuning.”

The first poster presentation received the Poster Award, and the second poster presentation won the Best Poster Award.