Author: users

Conference / Workshop

Symposium on VLSI Technology and Circuits 2025

by users

Dr. Quan Cheng, a Program-Specific Researcher, delivered a presentation on their research findings at the Symposium on VLSI Technology and Circuits 2025, which took place in Kyoto from June 8-12, 2025 (Presentation date June 12).

Q. Cheng, Q. Li, Z. Yang, Z. Kong, G. Niu, Y. Liang, J. Li, J. H. Park, W. Liao, H. Awano, T. Sato, L. Lin, and M. Hashimoto, “A Radiation-Hardened Neuromorphic Imager with Self-Healing Spiking Pixels and Unified Spiking Neural Network for Space Robotics,” Digest of Symposium on VLSI Technology and Circuits, 2025.

Event

Technicalr Seminar

by users

Four distinguished integrated circuit researchers visited our laboratory on June 9, 2025, to exchange ideas and deliver the following technical lectures:

Title: AI-Empowered Heterogeneous Computing for Physical Design Automation towards Timing Closure
Speaker: Prof. Yibo Lin (Peking University)

Title: Design-Agnostic Bi-Voltage Scaling for Efficient Cryo-CMOS DVFS
Speaker: Prof. Longyang Lin (Southern University of Science and Technology)

Title: Towards 2.5D/3D Composable Chiplets for AI Computing: Heterogenous Integration and Design Exploration
Speaker: Prof. Yu Kevin Cao (University of Minnesota)

Title: Co-Designing Algorithms and Hardware for Efficient Machine Learning System
Speaker: Prof. Caiwen Ding (University of Minnesota)

Publication

Publication at IACR TCHES

by users

The following paper has been published at IACR TCHES. This paper is a collaborative work with Tohoku University, NTT Social Informatics Laboratories, and NEC. The paper will be presented at International Conference on Cryptographic Hardware and Embedded Systems (CHES) in September 2025.

Rei Ueno, Akira Ito, Yosuke Todo, Akiko Inoue, Kazuhiko Minematsu, Hibiki Ishikawa, and Naofumi Homma, “All You Need is XOR-Convolution: A Generalized Higher-Order Side-Channel Attack with Application to XEX/XE-based Encryptions,” IACR Transactions on Cryptographic Hardware and Embedded Systems, 2025(3), pp. 317-360, 2025. https://doi.org/10.46586/tches.v2025.i3.317-360

Publication

Paper Accepted for Publication in IEEE Transactions on Device and Materials Reliability

by users

The following paper has been accepted for publication in IEEE Transactions on Device and Materials Reliability.

Shufan Xu, Kunyang Liu, Kiichi Niitsu and Hirofumi Shinohara, “Statistical Model and Transistor Size Effect of Hot Carrier Injection for Stability Reinforced SRAM Physically Unclonable Function,” IEEE Transactions on Device and Materials Reliability, doi: 10.1109/TDMR.2025.3574796.

Publication

Paper Accepted for Publication in IEEE Transactions on Electron Devices

by users

The following paper has been accepted for publication in IEEE Transactions on Electron Devices. This research is the result of a collaborative study with Kyoto Institute of Technology.

  • M. Shintani, K. Oishi, Y. Nishitani, H. Takayama, and T. Sato, “Comprehensive MOSFET capacitance characterization based on charge trajectories,” IEEE Transactions on Electron Devices, Vol.72, No.7, doi: 10.1109/TED.2025.3572874
Conference / Workshop

Paper accepted to MWSCAS 2025

by users

M1 Awano-Kun’s International Conference paper is accepted to IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), which will be held in Lansing, Michigan, USA, in August 2025.

Kei Awano, You Wu, Kento Okamura, Teruaki Ono, Kohei Sakamoto, Hiroaki Kitaike, Hironori Tagawa, Jin Nakamura, Masaya Kaneko, Yuta Kimura, Hiroaki Nakamura, Shufan Xu, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara, and Kiichi Niitsu, “A 110-mV 12-pW 0.00006-mm2 7-nm FinFET Self-Oscillating Voltage Doubler Using Vertically Implemented Back-End Metal-Oxide-Metal Capacitors For Small-Formfactor Up-Conversion”, to appear.

Conference / Workshop

Paper accepted to EUSIPCO 2025

by users

The following paper has been accepted to European Signal Processing Conference (EUSIPCO), which will be held in Palermo, Italy in September 2025.

C. Biesinger, H. Awano, and M. Hashimoto, “Window Function-Less DFT with Reduced Noise and Latency for Real-Time Music Analysis,” Proceedings of European Signal Processing Conference (EUSIPCO), to appear.

Conference / Workshop

Paper accepted to ISLPED 2025

by users

The following paper has been accepted to International Symposium on Low Power Electronics and Design (ISLPED), which will be held in Iceland in August 2025.

Q. Cheng, H. Zhang, Q. Li, Y. Liang, M. Zhang, Z. Chen, R. Zhang, J. Xiong, M. Huang, L. Lin, and M. Hashimoto, “A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators — Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation –,” Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), to appear.