Papers accepted for DAC2025

The following papers have been accepted to Design Automation Conference (DAC), to be held in San Francisco, CA, in Jun 2025.

  • Hiroto Tagata, Takashi Sato and Hiromitsu Awano, “Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline Accumulation,” Design Automation Conference (DAC), Jun 2025, to appear. (regular paper acceptance ratio: 420/1862=22.5%)
  • Xinyi Guo, Hiromitsu Awano and Takashi Sato, “Weighted Range-Constrained Ising-Model Decoder for Quantum Error Correction,” Design Automation Conference (DAC),Jun 2025, to appear. (regular paper acceptance ratio: 420/1862=22.5%)

IEEE EDS Japan Chapter Student Award (VLSI)

M1 Kitaike-Kun was awarded IEEE EDS Japan Chapter Student Award (VLSI)!

M1北池君がIEEE EDS Japan Chapter Student Award (VLSI)を受賞されました。

Hiroaki Kitaike, “A 0.9-2.6pW 0.1-0.25V 22nm 2-bit Supply-to-Digital Converter Using Always- Activated Supply-Controlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed Time-Stamped Bio-Recording”, IEEE EDS Japan Chapter Student Award (VLSI), Feb.2025.

Papers accepted in IEEE Transactions on Nuclear Science

The following papers have been accepted for publication in IEEE Transactions on Nuclear Science.

Yuibi Gomi, Kazusa Takami, Rurie Mizuno, Megumi Niikura, Ryuichi Yasuda, Yifan Deng, Shoichiro Kawase, Yukinobu Watanabe, Shin-ichiro Abe, Wang Liao, Motonobu Tampo, Soshi Takeshita, Koichiro Shimomura, Yasuhiro Miyake and Masanori Hashimoto, “Muon-Induced SEU Analysis and Simulation for Different Cell Types in 12-nm FinFET SRAMs, and 28-nm Planar SRAMs and Register Files,” in IEEE Transactions on Nuclear Science, doi: 10.1109/TNS.2025.3542468.

Kazusa Takami, Yuibi Gomi, Ryuichi Yasuda, Shin-ichiro Abe, Masatoshi Itoh, Hiroki Kanda, Mitsuhiro Fukuda and Masanori Hashimoto, “Validating Terrestrial SER in 12-, 28- and 65-nm SRAMs Estimated by Simulation Coupled with One-Time Neutron Irradiation,” in IEEE Transactions on Nuclear Science, doi: 10.1109/TNS.2025.3534564.

Seminar talk by Prof. Jaijeet Roychowdhury

The following seminar was held by Prof. Jaijeet Roychowdhury of U.C. Berkeley who visited the lab (2025/2/13).

“Oscillator and Latch Ising Machines”

Abstract
——–
For many real-world applications (ranging from large-scale networking and the design/verification of mission-critical systems to drug discovery and 5/6G wireless systems), modern society has become increasingly reliant on rapid and routine solution of hard discrete optimization problems.
Over the past decade, fascinating analog hardware approaches have arisen that combine principles of physics and computer science with optical, electronic and quantum engineering to solve combinatorial optimization problems in new ways—these have come to be known as Ising machines.
Such approaches leverage analog dynamics and physics to find good solutions of discrete optimization problems, potentially with advantages over traditional algorithms.
These approaches are based on the Ising model, a simple but powerful graph formulation with deep historical roots in physics using which combinatorial optimization problems can be represented.
While the first Ising machines relied on quantum mechanical interactions, newer schemes have emerged that are based on purely classical (non-quantum) operational mechanisms.
Classical Ising machine schemes that can be implemented on chip have many practical advantages—eg., smaller physical size, lower cost, lower energy consumption, on-chip integration, scaling to large problem sizes and mass production.
About seven years ago, we discovered that the analog dynamics of networks of electronic oscillators resulted in their solving Ising problems “naturally”.
A few years later, schemes that use bistable latches in analog operation were also devised.
This talk will cover the principles and practice of oscillator and latch Ising machines, touching on similarities and differences.
Surprisingly, a common mathematical framework based on Lyapunov functions helps explain these machines’ remarkable optimization properties.
The design and implementation of practical integrated circuits with analog Ising cores that deliver proper optimization performance will also be touched upon.
Another key focus will be Ising machine performance on real-world applications.
Examples will include the MU-MIMO detection problem in modern wireless communications—we will show how it can be converted to Ising form, and how well it is solved by analog Ising machine schemes.
Our results indicate that near-optimal symbol-error rates (SERs) are obtained, improving over the industrial state of the art by 20x for some scenarios.

Our paper accepted in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

The following paper has been accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

      

  • Sosei Ikeda, Hiromitsu Awano, and Takashi Sato, “Online training and inference system on edge FPGA using delayed feedback reservoir,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2025.3541565, available as early access.

ASP-DAC2025

At Asia and South Pacific Design Automation Conference (ASP-DAC 2025) held at the National Museum of Emerging Science and Innovation (Miraikan) in Japan from January 20 to January 23, 2025, the following members made presentation:

  • Masanori Hashimoto, Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi, Kozo Takeuchi, “ML-assisted SRAM Soft Error Rate Characterization: Opportunities and Challenges,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.379-384, January 2025.
  • Tomonari Tanaka, Takumi Uezono, Kohei Suenaga, Masanori Hashimoto, “Hardware Error Detection with In-Situ Monitoring of Control Flow-Related Specifications,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.966-973, January 2025.
  • Takuma Kawakami, Takashi Sato, Hiromitsu Awano, “Random Telegraph Noise Observed on 65-nm Bulk pMOS Transistors at 3.8K,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.1438-1443, January 2025.

Additionally, the following poster presentations were made during the co-located Work-in-Progress session:

  • Masami Utsunomiya, Hiroya Murata, Hiromitsu Awano, Takashi Sato, “Hardware Reservoir Using Transistor Variation Based on a 180nm Node Prototype Chip.”
  • Wakahiro Ohara, Takashi Sato, Hiromitsu Awano, “Cryo-CMOS Surface Code Decoder for Fault-Tolerant Quantum Computers.”
  • Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi, Kozo Takeuchi, Masanori Hashimoto, “Event-Wise Accurate Single-Event Upset Discrimination with Active Learning and Adaptive Hyperparameter Tuning.”

The first poster presentation received the Poster Award, and the second poster presentation won the Best Poster Award.

ASP-DAC 2025 Best Design Award

M1 Kitaike-Kun was awarded the Best Design Award at ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) 2025!

M1北池君がACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) 2025においてBest Design Awardを受賞されました。

Hiroaki Kitaike, Hironori Tagawa, Shufan Xu, Ruilin Zhang, Kunyang Liu and Kiichi Niitsu, “Design of 0.9-2.6p W 0.1-0.25V 22m 2-bit Supply-to-Digital Converter Using Always-Activated Supply-Controlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed Time-Stamped Bio-Recording”