At the International Conference on Computer Design (ICCD), held in Milan, Italy, from November 18 to 20, 2024, D2 student Zhang presented his research findings (presentation date: November 18).
M. Zhang, Q. Cheng, H. Awano, L. Lin, and M. Hashimoto, “S3M: Static Semi-Segmented Multipliers for Energy-Efficient DNN Inference Accelerators,” Proceedings of IEEE International Conference on Computer Design (ICCD), 2024.
The following paper has been accepted for DATE 2025. The results will be presented in Lyon in March 2025.
Quan Cheng, Wang Liao, Ruilin Zhang, Hao Yu, Longyang Lin and Masanori Hashimoto, HachiFI: A Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact Evaluation, Proc. Design, Automation and Test in Europe Conference (DATE), to appear.
At Design Gaia 2024, held in a hybrid format from November 12 to 14, 2024 (venue: Compal Hall in Oita City), M2 student Yoshida presented the following work (both oral and poster presentations were on the 12th).
The following paper has been accepted for publication in the IEEE Access Journal. This study was conducted in collaboration with OMRON Corporation.
R. Shirai, G. Nakao, and M. Hashimoto, “Analytical Equivalent Circuit Extraction of Foreign Metal Objects in WPT Systems,” IEEE Access Journal, DOI: 10.1109/ACCESS.2024.3500008 in press.
Dr. Zheyu Yan from the University of Notre Dame, who visited our laboratory, gave the following seminar talk (2024/10/24).
“Software-Hardware Co-Design of Neural Network Accelerators using Emerging Technologies”
