The paper below has been accepted for publication by IEEE Journal of Solid-State Circuits.
This research is a result of the CREST project on via-switch FPGA.
X. Bai, N. Banno, M. Miyamura, R. Nebashi, K. Okamoto, H. Numata, N. Iguchi, M. Hashimoto, T. Sugibayashi, T. Sakamoto, and M. Tada, “Via-Switch FPGA: 65nm CMOS Implementation and Evaluation,” IEEE Journal of Solid-State Circuits, in press.
The following papers have benn accepted for publication by IEICE Transactions on Fundamentals. These works were carried out at Osaka University with Nagoya University and Socionext Inc.
T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, “Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, in press.
Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, “Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, in press.
The following paper has been accepted for publication in IEEE Transactions on Information Forensics and Security (TIFS).
This work is a joint research with Nanjing University of Aeronautics and Astronautics.
Song Bian, Dur E Shahwar Kundi, Kazuma Hirozawa, Weiqiang Liu, and Takashi Sato, “APAS: Application-specific accelerators for RLWE-based homomorphic linear transformations,” IEEE Transactions on Information Forensics and Security (TIFS), accepted for publication.
The paper below has been accepted by IEEE Transactions on Nuclear Science (TNS). The first author is Mr. Ito who graduated from Osaka University in March 2021. This paper presents the result of the joint research project with Hitachi Ltd.
K. Ito, Y. Zhang, H. Itsuji, T. Uezono, T. Toba, and M. Hashimoto, “Analyzing DUE Errors on GPUs with Neutron Irradiation Test and Fault Injection to Control Flow,” IEEE Transactions on Nuclear Science, in Early Access.
Two papers below are published in IEEE Transactions on Nuclear Science. The first paper of Dr. Kato is attributed to the joint work with Socionext Inc. and the JST OPERA project. The second paper of Dr. Liao is attributed to the projects of JST OPERA, JSPS Kakenhi Kiban(S), and the joint work with Socionext Inc.
T. Kato, M. Tampo, S. Takeshita, H. Tanaka, H. Matsuyama, M. Hashimoto, and Y. Miyake, “Muon-Induced Single-Event Upsets in 20-nm SRAMs: Comparative Characterization with Neutrons and Alpha Particles,” IEEE Transactions on Nuclear Science, 68(7), pp. 1436-1444, July 2021.
W. Liao, K. Ito, S. Abe, Y. Mitsuyama, and M. Hashimoto, “Characterizing Energetic Dependence of Low-energy Neutron-induced SEU and MCU and Its Influence on Estimation of Terrestrial SER in 65 nm Bulk SRAM,” IEEE Transactions on Nuclear Science, 68(6), pp. 1228-1234, June 2021.
The following paper has been accepted for publication in IEEE Transactions on Power Electronics (TPEL).