Paper Accepted for Publication in IEEE Solid-State Circuits Letters

The paper below has been accepted by IEEE Solid-State Circuits Letters.

Y. Gomi, A. Sato, W. Madany, K. Okada, S. Adachi, M. Itoh, and M. Hashimoto, “A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement,” in IEEE Solid-State Circuits Letters, doi: 10.1109/LSSC.2025.3589611.