The following paper has been accepted for publication in the IEEE Sensors Journal and is now available for early access.
The paper is about the design of organic memory circuits, improving the stability and reliability.
The following paper has been accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). This paper is a summary of the research results developed by a former student of our laboratory, who further extended the results of his research when he was a master’s course student.
The following paper has been accepted for publication in Japanese Journal of Applied Physics (JJAP). This is a joint work with Rohm Co. Ltd.
The following paper has been accepted for publication in Japanese Journal of Applied Physics (JJAP). This is an outcome of the joint work with National Institute of Advanced Industrial Science.
The research results of the joint research with Kochi University of Technology conducted within the framework of OPERA will be published in IEEE Transactions on Nuclear Science.
T. Tanaka, W. Liao, M. Hashimoto, and Y. Mitsuyama, “Impact of Neutron-Induced SEU in FPGA CRAM on Image-Based Lane Tracking for Autonomous Driving: from Bit Upset to SEFI and Erroneous Behavior,” IEEE Transactions on Nuclear Science, accepted for publication.
IThe following paper has been accepted for publication in IEEE Transactions on Power Electronics (TPEL).
Michihiro Shintani, Aoi Ueda, and Takashi Sato, “Accelerating Parameter Extraction of Power MOSFET Models Using Automatic Differentiation,” IEEE Transactions on Power Electronics (TPEL), (accepted for publication).
The paper below has been accepted by Transactions of the Virtual Reality Society of Japan. The first author is Ms. Suzunaga who completed master’s degree at Osaka University in March 2021. This work was carried out at Osaka University with Tohoku University,
S. Suzunaga, K. Fujita, R. Shirai, and Y. Itoh, “CoiLED Display: Striped Flexible Displays Windable Around Objects, ” Transactions of the Virtual Reality Society of Japan (in Japanese), accepted, to appear.
The paper below has been accepted for publication by IEEE Journal of Solid-State Circuits.
This research is a result of the CREST project on via-switch FPGA.
X. Bai, N. Banno, M. Miyamura, R. Nebashi, K. Okamoto, H. Numata, N. Iguchi, M. Hashimoto, T. Sugibayashi, T. Sakamoto, and M. Tada, “Via-Switch FPGA: 65nm CMOS Implementation and Evaluation,” IEEE Journal of Solid-State Circuits, in press.
The following papers have benn accepted for publication by IEICE Transactions on Fundamentals. These works were carried out at Osaka University with Nagoya University and Socionext Inc.
T. Cheng, Y. Masuda, J. Nagayama, Y. Momiyama, J. Chen, and M. Hashimoto, “Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, in press.
Y. Masuda, J. Nagayama, T. Cheng, T. Ishihara, Y. Momiyama, and M. Hashimoto, “Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling,” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, in press.
The following paper has been accepted for publication in IEEE Transactions on Information Forensics and Security (TIFS).
This work is a joint research with Nanjing University of Aeronautics and Astronautics.
Song Bian, Dur E Shahwar Kundi, Kazuma Hirozawa, Weiqiang Liu, and Takashi Sato, “APAS: Application-specific accelerators for RLWE-based homomorphic linear transformations,” IEEE Transactions on Information Forensics and Security (TIFS), accepted for publication.