At Asia and South Pacific Design Automation Conference (ASP-DAC 2025) held at the National Museum of Emerging Science and Innovation (Miraikan) in Japan from January 20 to January 23, 2025, the following members made presentation:
- Masanori Hashimoto, Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi, Kozo Takeuchi, “ML-assisted SRAM Soft Error Rate Characterization: Opportunities and Challenges,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.379-384, January 2025.
- Tomonari Tanaka, Takumi Uezono, Kohei Suenaga, Masanori Hashimoto, “Hardware Error Detection with In-Situ Monitoring of Control Flow-Related Specifications,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.966-973, January 2025.
- Takuma Kawakami, Takashi Sato, Hiromitsu Awano, “Random Telegraph Noise Observed on 65-nm Bulk pMOS Transistors at 3.8K,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.1438-1443, January 2025.
Additionally, the following poster presentations were made during the co-located Work-in-Progress session:
- Masami Utsunomiya, Hiroya Murata, Hiromitsu Awano, Takashi Sato, “Hardware Reservoir Using Transistor Variation Based on a 180nm Node Prototype Chip.”
- Wakahiro Ohara, Takashi Sato, Hiromitsu Awano, “Cryo-CMOS Surface Code Decoder for Fault-Tolerant Quantum Computers.”
The first poster presentation received the Poster Award, and the second poster presentation won the Best Poster Award.
