The paper below has been accepted for publication by IEEE Journal of Solid-State Circuits.
This research is a result of the CREST project on via-switch FPGA.
X. Bai, N. Banno, M. Miyamura, R. Nebashi, K. Okamoto, H. Numata, N. Iguchi, M. Hashimoto, T. Sugibayashi, T. Sakamoto, and M. Tada, “Via-Switch FPGA: 65nm CMOS Implementation and Evaluation,” IEEE Journal of Solid-State Circuits, in press.
