The following paper has been accepted for presentation at the IEEE Custom Integrated Circuits Conference (CICC) 2025. We will be presenting our findings in Boston in April.
Q. Cheng, Q. Li, W. Dong, M. Zhang, R. Zhang, M. Huang, H. Yu, Y. Shi, H. Awano, T. Sato, L. Lin, and M. Hashimoto, “A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-On-Chip Towards In-Orbit Computing,” Proceedings of IEEE Custom Integrated Circuits Conference (CICC), to appear.
Dr. Mehdi Saligane from the University of Michigan, who visited our laboratory, presented the following seminar on December 27, 2024:
“What is Possible with Open Design?”
Sorry, this entry is only available in 日本語.
The following paper has been published from IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES). This is an outcome of collaborative research with Tohoku University and NTT Social Informatics Laboratories. This results will be also presented at International Conference on Cryptographic Hardware and Embedded Systems (CHES) at September 2025.
Akira Ito, Rei Ueno, and Naofumi Homma, “Perceived Information Revisited II: Information-Theoretical Analysis of Deep-learning Based Side-Channel Attacks,” IACR Transactions on Cryptographic Hardware and Embedded Systems, Vol. 2025, No. 1, pp. 450–474, DOI: https://doi.org/10.46586/tches.v2025.i1.450-474, Dec 2024.
Prof. Sato gave an invited talk at International Display Workshops (IDW) 2024 held at the Sapporo International Convention Center from December 4 to 6, 2024. (The invited talk was on December 5).
In A-SSCC 2024, which was held at the Hiroshima International Conference Center from November 18 to 21, 2024, Prof. Sato participated as one of the panelists in the panel discussion “AI-Driven IC Design: Opportunities and Challenges”. (The panel discussion was held on November 20).
Quan Cheng, who completed their doctoral program in September 2024, presented the following paper (presentation date: November 20).
Q. Cheng, L. Lin, M. Huang, Q. Li, Z. Yang, L. Dai, H. Yu, Y. Chen, Y. Shi, and M. Hashimoto, “A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping,” Technical Digest of Asian Solid-State Circuits Conference (A-SSCC), 2024.
At the International Conference on Computer Design (ICCD), held in Milan, Italy, from November 18 to 20, 2024, D2 student Zhang presented his research findings (presentation date: November 18).
M. Zhang, Q. Cheng, H. Awano, L. Lin, and M. Hashimoto, “S3M: Static Semi-Segmented Multipliers for Energy-Efficient DNN Inference Accelerators,” Proceedings of IEEE International Conference on Computer Design (ICCD), 2024.
The following paper has been accepted for DATE 2025. The results will be presented in Lyon in March 2025.
Quan Cheng, Wang Liao, Ruilin Zhang, Hao Yu, Longyang Lin and Masanori Hashimoto, HachiFI: A Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact Evaluation, Proc. Design, Automation and Test in Europe Conference (DATE), to appear.
At Design Gaia 2024, held in a hybrid format from November 12 to 14, 2024 (venue: Compal Hall in Oita City), M2 student Yoshida presented the following work (both oral and poster presentations were on the 12th).
The following paper has been accepted for publication in the IEEE Access Journal. This study was conducted in collaboration with OMRON Corporation.
R. Shirai, G. Nakao, and M. Hashimoto, “Analytical Equivalent Circuit Extraction of Foreign Metal Objects in WPT Systems,” IEEE Access Journal, DOI: 10.1109/ACCESS.2024.3500008 in press.