2025年3月31日から4月2日にフランスのリヨンで開催された Design, Automation and Test in Europe Conference (DATE 2025)において、橋本が研究成果の発表を行いました(発表日は2025/4/2)。
Q. Cheng, W. Liao, R. Zhang, H. Yu, L. Lin, and M. Hashimoto, “HachiFI: a Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact Evaluation,” Proceedings of Design, Automation and Test in Europe Conference (DATE), March 2025.
IEEE Sensors Journal へ以下の論文の採録が決定しました。
Ryota Fukugasako, Hisafumi Asaue, Tomoki Shiotani, Masanori Hashimoto, and Ryo Shirai, “A Current Chopper-assisted Magnetic Field-based Backscatter Communication Method with WPT Overcoming Ultra-low Coupling Coefficients,” in IEEE Sensors Journal, doi: 10.1109/JSEN.2025.3555072.
M1北池君が令和6年度京都大学総長賞を受賞されました。
新津教授が総務省 戦略的情報通信研究開発推進事業(SCOPE)において成果展開推進賞を受賞されました。
2025年2月27-3月4日に米国アリゾナ州ツーソンで開催された IEEE/CVF Winter Conference on Applications of Computer Vision (WACV) にて、D2の 張 少雄くんが研究成果の発表を行いました (発表日は3月1日)。
以下の論文が、2025年6月に米国カリフォルニア州San Franciscoで開催予定のDesign Automation Conference (DAC) に採択されました。
M1 Kitaike-Kun was awarded IEEE EDS Japan Chapter Student Award (VLSI)!
M1北池君がIEEE EDS Japan Chapter Student Award (VLSI)を受賞されました。
Hiroaki Kitaike, “A 0.9-2.6pW 0.1-0.25V 22nm 2-bit Supply-to-Digital Converter Using Always- Activated Supply-Controlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed Time-Stamped Bio-Recording”, IEEE EDS Japan Chapter Student Award (VLSI), Feb.2025.
IEEE Transactions on Nuclear Science へ以下の論文が採録されました。
Yuibi Gomi, Kazusa Takami, Rurie Mizuno, Megumi Niikura, Ryuichi Yasuda, Yifan Deng, Shoichiro Kawase, Yukinobu Watanabe, Shin-ichiro Abe, Wang Liao, Motonobu Tampo, Soshi Takeshita, Koichiro Shimomura, Yasuhiro Miyake and Masanori Hashimoto, “Muon-Induced SEU Analysis and Simulation for Different Cell Types in 12-nm FinFET SRAMs, and 28-nm Planar SRAMs and Register Files,” in IEEE Transactions on Nuclear Science, doi: 10.1109/TNS.2025.3542468.
Kazusa Takami, Yuibi Gomi, Ryuichi Yasuda, Shin-ichiro Abe, Masatoshi Itoh, Hiroki Kanda, Mitsuhiro Fukuda and Masanori Hashimoto, “Validating Terrestrial SER in 12-, 28- and 65-nm SRAMs Estimated by Simulation Coupled with One-Time Neutron Irradiation,” in IEEE Transactions on Nuclear Science, doi: 10.1109/TNS.2025.3534564.
研究室を訪問したU.C. BerkeleyのProf. Jaijeet Roychowdhuryによる、以下のセミナーを開催しました (2025/2/13)。
“Oscillator and Latch Ising Machines”
Abstract
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For many real-world applications (ranging from large-scale networking and the design/verification of mission-critical systems to drug discovery and 5/6G wireless systems), modern society has become increasingly reliant on rapid and routine solution of hard discrete optimization problems.
Over the past decade, fascinating analog hardware approaches have arisen that combine principles of physics and computer science with optical, electronic and quantum engineering to solve combinatorial optimization problems in new ways—these have come to be known as Ising machines.
Such approaches leverage analog dynamics and physics to find good solutions of discrete optimization problems, potentially with advantages over traditional algorithms.
These approaches are based on the Ising model, a simple but powerful graph formulation with deep historical roots in physics using which combinatorial optimization problems can be represented.
While the first Ising machines relied on quantum mechanical interactions, newer schemes have emerged that are based on purely classical (non-quantum) operational mechanisms.
Classical Ising machine schemes that can be implemented on chip have many practical advantages—eg., smaller physical size, lower cost, lower energy consumption, on-chip integration, scaling to large problem sizes and mass production.
About seven years ago, we discovered that the analog dynamics of networks of electronic oscillators resulted in their solving Ising problems “naturally”.
A few years later, schemes that use bistable latches in analog operation were also devised.
This talk will cover the principles and practice of oscillator and latch Ising machines, touching on similarities and differences.
Surprisingly, a common mathematical framework based on Lyapunov functions helps explain these machines’ remarkable optimization properties.
The design and implementation of practical integrated circuits with analog Ising cores that deliver proper optimization performance will also be touched upon.
Another key focus will be Ising machine performance on real-world applications.
Examples will include the MU-MIMO detection problem in modern wireless communications—we will show how it can be converted to Ising form, and how well it is solved by analog Ising machine schemes.
Our results indicate that near-optimal symbol-error rates (SERs) are obtained, improving over the industrial state of the art by 20x for some scenarios.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems へ以下の論文が採録されました。