The following two research presentations were delivered at the ACM/IEEE Design Automation Conference (DAC) 2025, held in San Francisco, USA, from June 22 to June 25, 2025. The presentations were given on June 23 (Guo) and June 24 (Tagata), respectively. DAC is a premier conference in the field of integrated circuit design.
- X. Guo, H. Awano, and T. Sato, “Weighted Range-Constrained Ising-Model Decoder for
Quantum Error Correction,” in Proc. ACM/IEEE Design Automation Conference (DAC), pp.1-6, July 2025. - H. Tagata, T. Sato, and H. Awano, “Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline Accumulation,” in Proc. ACM/IEEE Design Automation Conference (DAC), pp.1-6, July 2025.
