D2 Xu-San’s International Conference paper is accepted to IEEE International A-SSCC (Asian Solid-State Circuits Conference) Conference.
The results will be presented in Daejeon in November.
“A Less than 6.5E−8 BER 36-Way Reconfigurable PUF with 4-bit Stable Responses per Cell Featuring Machine Learning-Based Best-Configuration Selection”
Authors: Shufan Xu*, Kunyang Liu*, Nan Wang, Hirofumi Shinohara and Kiichi Niitsu (*Equally Credited Authors)
M1 Okamura-Kun’s International Conference paper is accepted to IEEE International ICECS (International Conference on Electronics Circuits and Systems) Conference.
The results will be presented in Marrakech in November.
“A 22nm CMOS 0.26nW-Standby-Power 37GHz Ingestible OOK Transmitter for Digital Pills”
Authors: Kento Okamura, Takeshi Fujiyabu, Hisataka Maruyama, Kei Awano, You Wu, Hiroaki Kitaike, Jin Nakamura, Masaya Kaneko, Yuta Kimura, Hiroaki Nakamura, Shufan Xu, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara, Daisuke Anzai, Natsuko Inagaki, Taichi Ito and Kiichi Niitsu
M1 Awano-Kun’s International Conference paper is accepted to IEEE International APCCAS (Asia Pacific Conference on Circuits and Systems) Conference.
The results will be presented in Busan in October.
“65nm 0.0736mm2/Pixel Simultaneous Energy-Harvesting-and-Sensing 2-by-2 Self-Powered CMOS Image Sensor Pixel Array Using Self-Oscillating Voltage Doubler for Thermal-Aware Zero-Stand-by-Power Imaging”
Authors: Kei Awano, Yoshitsune Sugimura, Yuma Ota, You Wu, Keishi Ogura, Hiroaki Kitaike, Kento Okamura, Shufan Xu, Jin Nakamura, Masaya Kaneko, Yuta Kimura, Hiroaki Nakamura, Ruilin Zhang, Hirofumi Shinohara, Kunyang Liu and Kiichi Niitsu
Graduate Student Wu-Kun’s paper won the Best Design Award at the ISLPED 2025 Design Contest.
“A Sub-10Hz Sub-nW 65nm CMOS Timer with Voltage-Stacking of an Oscillator and Frequency Dividers for Small-Formfactor Scaling-Friendly IoTs”
Authors：You Wu, Hiroaki Kitaike, and Kiichi Niitsu
Rei Ueno gave a spotlight talk about information-theoretical analysis of side-channel attacks at Information-Theoretic Cryptography Conference (ITC) 2025, affiliated event of CRYPTO 2025, in UCSB, USA, on August 16th.
Akira Ito, Rei Ueno, and Naofumi Homma, “Information-Theoretical Analysis of Side-Channel Attack and Its Countermeasure,” Information-Theoretic Cryptography Conference (ITC), 2025.
Mr. Zhang, a D2 student, presented the paper at the IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED 2025) held at the University of Iceland from August 6-8, 2025 (presentation date August 7).
Q. Cheng, H. Zhang, Q. Li, Y. Liang, M. Zhang, Z. Chen, R. Zhang, J. Xiong, M. Huang, L. Lin, and M. Hashimoto, “A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators — Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation –,” Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), August 2025.
M2 Kitaike-Kun was awarded NEWCAS Young Professional Paper Award 2nd place at 23RD IEEE INTERNATIONAL NEWCAS CONFERENCE 2025!
The paper below has been accepted by IEEE Solid-State Circuits Letters.
Y. Gomi, A. Sato, W. Madany, K. Okada, S. Adachi, M. Itoh, and M. Hashimoto, “A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement,” in IEEE Solid-State Circuits Letters, doi: 10.1109/LSSC.2025.3589611.
This paper, a collaborative research outcome with Hitachi, Ltd., has been accepted by IEEE Access.
H. Itsuji, T. Uezono, T. Toba, K. Ito and M. Hashimoto, “A Hardware-Aware Failure-Detection Method for GPU Control-Logic,” in IEEE Access, vol. 13, pp. 113890-113904, 2025, doi: 10.1109/ACCESS.2025.3584759.
The following paper has been accepted at ICCAD (International Conference on Computer-Aided Design) 2025. The results will be presented in Munich in October.