投稿者: users

Publication

IEEE Transactions on Nuclear Science 採録決定

by users

IEEE Transactions on Nuclear Science へ以下の論文が採録されました。

Yuibi Gomi, Kazusa Takami, Rurie Mizuno, Megumi Niikura, Ryuichi Yasuda, Yifan Deng, Shoichiro Kawase, Yukinobu Watanabe, Shin-ichiro Abe, Wang Liao, Motonobu Tampo, Soshi Takeshita, Koichiro Shimomura, Yasuhiro Miyake and Masanori Hashimoto, “Muon-Induced SEU Analysis and Simulation for Different Cell Types in 12-nm FinFET SRAMs, and 28-nm Planar SRAMs and Register Files,” in IEEE Transactions on Nuclear Science, doi: 10.1109/TNS.2025.3542468.

Kazusa Takami, Yuibi Gomi, Ryuichi Yasuda, Shin-ichiro Abe, Masatoshi Itoh, Hiroki Kanda, Mitsuhiro Fukuda and Masanori Hashimoto, “Validating Terrestrial SER in 12-, 28- and 65-nm SRAMs Estimated by Simulation Coupled with One-Time Neutron Irradiation,” in IEEE Transactions on Nuclear Science, doi: 10.1109/TNS.2025.3534564.

Event

Jaijeet Roychowdhury教授講演会

by users

研究室を訪問したU.C. BerkeleyのProf. Jaijeet Roychowdhuryによる、以下のセミナーを開催しました (2025/2/13)。

“Oscillator and Latch Ising Machines”

Abstract
——–
For many real-world applications (ranging from large-scale networking and the design/verification of mission-critical systems to drug discovery and 5/6G wireless systems), modern society has become increasingly reliant on rapid and routine solution of hard discrete optimization problems.
Over the past decade, fascinating analog hardware approaches have arisen that combine principles of physics and computer science with optical, electronic and quantum engineering to solve combinatorial optimization problems in new ways—these have come to be known as Ising machines.
Such approaches leverage analog dynamics and physics to find good solutions of discrete optimization problems, potentially with advantages over traditional algorithms.
These approaches are based on the Ising model, a simple but powerful graph formulation with deep historical roots in physics using which combinatorial optimization problems can be represented.
While the first Ising machines relied on quantum mechanical interactions, newer schemes have emerged that are based on purely classical (non-quantum) operational mechanisms.
Classical Ising machine schemes that can be implemented on chip have many practical advantages—eg., smaller physical size, lower cost, lower energy consumption, on-chip integration, scaling to large problem sizes and mass production.
About seven years ago, we discovered that the analog dynamics of networks of electronic oscillators resulted in their solving Ising problems “naturally”.
A few years later, schemes that use bistable latches in analog operation were also devised.
This talk will cover the principles and practice of oscillator and latch Ising machines, touching on similarities and differences.
Surprisingly, a common mathematical framework based on Lyapunov functions helps explain these machines’ remarkable optimization properties.
The design and implementation of practical integrated circuits with analog Ising cores that deliver proper optimization performance will also be touched upon.
Another key focus will be Ising machine performance on real-world applications.
Examples will include the MU-MIMO detection problem in modern wireless communications—we will show how it can be converted to Ising form, and how well it is solved by analog Ising machine schemes.
Our results indicate that near-optimal symbol-error rates (SERs) are obtained, improving over the industrial state of the art by 20x for some scenarios.

Publication

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems採録決定

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems へ以下の論文が採録されました。

    　　

  • Sosei Ikeda, Hiromitsu Awano, and Takashi Sato, “Online training and inference system on edge FPGA using delayed feedback reservoir,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2025.3541565, available as early access.
Conference / Workshop

SCIS2025

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2025年1月28日から1月31日にリーガロイヤルホテル小倉で開催された暗号と情報セキュリティシンポジウム（SCIS2025）にて、松岡と永井が研究発表を行いました。

  • 松岡 航太郎, 辺 松, 佐藤 高史, “GGPinReal: LWEを用いたGarbled CircuitとTFHEによる検証可能論理回路秘匿演算基盤,” 暗号とセキュリティシンポジウム, pp.1-8, January 2025.
  • 永井 寿弥, 松岡 航太郎, 佐藤 高史, “TFHEとB/FV-big-numberを用いた秘匿計算に向けた暗号方式間相互変換手続きの提案,” 暗号とセキュリティシンポジウム, pp.1-8, January 2025.
Announcement

3回生（研究室配属対象者）向け研究室説明会2025

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集積システム工学講座では，2025年2月20日(木曜)に研究室説明会を行います．

日時：2025年2月20日(木曜) 13:00-15:30
集合場所: 総合研究9号館北棟 2階N2講義室
進め方: 最初の20-30分が全体説明で、その後3つのグループに分かれて3研究室を順に見学します。

本説明会は本学電気電子工学科における研究室配属対象者向けであり，対象者以外は参加できません．

Conference / Workshop

SCAIS 2025　招待講演

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上野が小倉で開催されたSmall-workshop on Communications between Academia and Industry for Security (SCAIS) で招待講演を行いました．

上野嶺，”サイドチャネル攻撃の定量的評価と対策技術,” Small-workshop on Communications between Academia and Industry for Security (SCAIS)，2025年1月27日．

Award/Conference / Workshop

ASP-DAC2025

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2025年1月20日から1月23日に日本科学未来館で開催されたAsia and South Pacific Design Automation Conference (ASP-DAC 2025)において、以下のメンバーが研究成果の発表を行いました。

  • Masanori Hashimoto, Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi, Kozo Takeuchi, “ML-assisted SRAM Soft Error Rate Characterization: Opportunities and Challenges,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.379-384, January 2025.
  • Tomonari Tanaka, Takumi Uezono, Kohei Suenaga, Masanori Hashimoto, “Hardware Error Detection with In-Situ Monitoring of Control Flow-Related Specifications,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.966-973, January 2025.
  • Takuma Kawakami, Takashi Sato, Hiromitsu Awano, “Random Telegraph Noise Observed on 65-nm Bulk pMOS Transistors at 3.8K,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.1438-1443, January 2025.

付随して開催されたWork-in-Progressセッションにおいて以下のポスター発表を行いました。

  • Masami Utsunomiya, Hiroya Murata, Hiromitsu Awano, Takashi Sato, “Hardware Reservoir Using Transistor Variation Based on a 180nm Node Prototype Chip.”
  • Wakahiro Oh, Takashi Sato, Hiromitsu Awano, “Cryo-CMOS Surface Code Decoder for Fault-Tolerant Quantum Computers.”
  • Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi, Kozo Takeuchi, Masanori Hashimoto, “Event-Wise Accurate Single-Event Upset Discrimination with Active Learning and Adaptive Hyperparameter Tuning.”

1件目の発表がPoster Awardを、2件目の発表がBest Poster Awardを受賞しました。

Conference / Workshop

CICC 2025 論文採択

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以下の論文が IEEE Custom Integrated Circuits Conference (CICC) 2025 に採択されました。4月にボストンで成果を発表します。

Q. Cheng, Q. Li, W. Dong, M. Zhang, R. Zhang, M. Huang, H. Yu, Y. Shi, H. Awano, T. Sato, L. Lin, and M. Hashimoto, “A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-On-Chip Towards In-Orbit Computing,” Proceedings of IEEE Custom Integrated Circuits Conference (CICC), to appear.